1. Field of the Invention
The present invention relates to noise reduction for integrated circuits (ICs), and more particularly to reducing the noise on the input line of a driver.
2. Description of Related Art
Digital logic circuits have increased in speed and complexity by using lower voltages and smaller logic elements. As the voltage of logic elements has decreased, the noise margins of logic elements have also decreased. Furthermore, fast logic circuit designs, such as domino circuits, have an increased noise susceptibility. Therefore, the faster logic elements have become more susceptible to erroneous activation or deactivation due to noise on the signal lines driving the logic elements.
FIG. 1 shows a typical circuit with output terminal 111 of first logic element 110 driving signal line 120 to input terminal 132 of second logic element 130. The logic elements and signal lines can be on a printed circuit board or a semiconductor chip. Furthermore, the logic elements can be for example drivers, inverters, AND gates, OR gates, NAND gates, NOR gates, flip-flops, latches, microprocessors, or memories.
A primary cause of noise on signal line 120 is crosstalk noise from adjacent signal lines. As shown in FIG. 2, signal line 120 develops a crosstalk capacitance Cx, represented by capacitor 240 and capacitor 250, with signal line 210 and signal line 230. Due to crosstalk capacitance Cx, when signal lines 210 or signal line 230 switches states some crosstalk noise is introduced onto signal line 120. The crosstalk noise on signal line 120 can cause erroneous activation or deactivation of second logic element 130 (FIG. 1).
Typically, crosstalk noise has been minimized using routing techniques. For example, as shown in FIG. 3(a), signal line 210, signal line 120, and signal line 230 can be routed further apart to minimize the crosstalk capacitance. For even greater crosstalk suppression, ground or power lines, such as ground line 315 or power line 325, can be routed between signal lines 210, signal line 120, and signal line 230, as shown in FIG. 3(b). Since the ground lines and power lines do not switch states in normal operation, the power lines and ground lines do not produce any crosstalk noise. Furthermore, ground line 315 and power line 325 shield signal line 120 from noise on signal line 210 and signal line 230.
Although routing techniques can substantially reduce crosstalk problems, typically, the routing techniques greatly increases the board area or semiconductor chip area required for the signal lines. The increase in board area or chip area increases the cost of a digital system or chip. In addition, the size of many logic blocks in VLSI circuits are dictated by the area of the signal lines rather than the area of transistors. Therefore, routing techniques which would further increase the area of the signal lines are very costly and not recommended in these logic blocks. Furthermore, these routing techniques do not provide noise suppression for other types of noise such as ground bounce (as described below).
FIG. 4 shows an example transistor level diagram of first logic element 110, signal line 120, and second logic element 130. In the example of FIG. 4, first logic element 110 is a static inverter 110-4 formed by PMOS transistor 403 and NMOS transistor 406. Second logic element 130 is a CMOS domino driver 130-4. Voltage supply 410 represents the ground bounce voltage Vgroundbounce, i.e. the difference between the actual voltage level of ground at first logic element 110 and second logic element 130.
CMOS domino driver 130-4 is selected in this example since the CMOS domino logic family is extremely sensitive to noise on the incoming signal line. CMOS domino logic elements are clocked elements requiring a precharge interval and an evaluation interval. During the precharge interval, when clock signal CLK is at a logic low level, the output node of the CMOS domino logic element is charged to a logic high level. During the evaluation interval, when clock signal CLK is at a logic high level, the output node is either discharged to reach logic low or remains at logic high depending on the inputs to the CMOS domino logic element.
Specifically, in CMOS domino driver 130-4, during the precharge interval, when clock signal CLK is at logic low, PMOS transistor 413 precharges output node 416 to a logic high level. During the evaluation interval, if input signal IN on signal line 120 is at logic high, the charge on output node 416 can be discharged to ground through input NMOS transistor 419 and clocked NMOS transistor 422, so that output node 416 transitions to logic low. However, if input signal IN on signal line 120 is at logic low, the charge on output node 416 is not discharged, so that output node 416 remains at logic high. Output inverter 420 provides output signal OUT by inverting the signal on output node 416.
The particular embodiment of CMOS domino driver 130-4 shown in FIG. 4, includes an optional feedback latch formed by feedback inverter 430, feedback PMOS transistor 440, and feedback NMOS transistor 450. During the precharge interval output node 416 is at logic high; therefore feedback PMOS transistor 440 is activated and maintains output node 416 at logic high. Input NMOS transistor 419 and clocked NMOS transistor 422 have a greater current sinking strength than the current sourcing strength of feedback PMOS transistor 440 so that input NMOS transistor 419 and clocked NMOS transistor 422 are able to discharge output node 416. During the evaluation interval, if input signal IN on signal line 120 is at logic high, output node 416 is forced to logic low by input NMOS transistor 419 and clocked NMOS transistor 422. Feedback PMOS transistor 440 is deactivated when output node 416 goes to logic low. Feedback PMOS transistor 440 is sized so that feedback PMOS transistor 440 can balance the effect of leakage through input NMOS transistor 419 and clocked NMOS transistor 422 without unduly slowing the discharge of output node 416.
CMOS domino driver 130-4 is particularly susceptible to noise, that causes input signal IN on signal line 120 to have a higher voltage than ground when input signal IN should be at logic low. For example if signal line 210 (FIG. 2) were to transition for logic low to logic high, while signal line 120 is at logic low, a momentary spike may appear on signal line 120 due to the effect of the crosstalk capacitance Cx. Even a momentary spike of sufficient voltage on signal line 120 during the evaluation interval can partially activate input NMOS transistor 419 resulting in the discharge of output node 416. Even though NMOS transistor 419 is deactivated after the spike output node 416 is not recharged until the next precharge interval; therefore, CMOS domino driver 130-4 incorrectly outputs a logic high instead of a logic low during the current evaluation interval.
Furthermore, the ground bounce problem represented by voltage supply 410 compounds the noise problem. If the ground voltage at logic static inverter 110-4 is at a positive ground bounce voltage Vgroundbounce above voltage of the ground signal at CMOS domino driver 130-4 and static inverter 110-4 is attempting to drive input signal IN to a logic low level then input signal IN is only driven to the ground bounce voltage Vgroundbounce instead of the ground level as expected by CMOS domino driver 130-4. Therefore, even a very low voltage noise spike signal line 120 can partially activate input NMOS transistor 419.
As mentioned above routing techniques have been used to reduce the noise problem. However routing techniques are too expensive in terms of board area or semiconductor die area. Furthermore, the routing techniques have no effect on the ground bounce problem. Therefore, some circuit techniques have been developed to attempt to suppress noise on a signal line.
The most common technique is to increase the current sourcing strength and current sinking strength of the driver. For the circuit of FIG. 4, the current sinking strength of NMOS transistor 406 on signal line 120 is increased using well known techniques. Thus as a noise spike is developed on signal line 120, NMOS transistor 406 is able to sink the noise to ground. However, if signal line 120 is long, the inherent resistance of signal line 120 increases. As the resistance of signal line 120 increases, the time required for NMOS transistor 406 to sink the noise on signal line 120 also increases. Therefore, if signal line 120 is long increasing the current sinking strength of NMOS transistor 406 does not prevent the partial activation of input NMOS transistor 419 due to noise spikes. Moreover, increasing the current sinking strength of NMOS transistor 406 entails increasing the load to the driver of NMOS transistor 406 which would increase the switching time of static inverter 110-4. Furthermore, increasing the current sinking strength of NMOS transistor 406 has no effect on the ground bounce problem, since signal line 120 is only pulled to the ground bounce voltage Vgroundbounce.
Another circuit technique to reduce the impact noise spikes on signal line 120 is to increase the current sourcing strength of feedback PMOS transistor 440. As explained above, feedback PMOS transistor 440 is present to offset leakage current through input NMOS transistor 419 and clocked NMOS transistor 422. By increasing the current sourcing strength of feedback PMOS transistor 440, feedback PMOS transistor 440 is able to offset the partial activation of input NMOS transistor 419 due to noise spikes on signal line 120. However, the increasing the current sourcing strength of feedback PMOS transistor 440 enough to offset noise spikes significantly slows the discharge of output node 416 under normal operation. Moreover, increasing the current sourcing strength of feedback PMOS transistor 440 increases the short circuit current, which increases power consumption, during the evaluation interval if input NMOS transistor 419 and clocked NMOS transistor 422 are activated. Furthermore, increasing the current sourcing strength of feedback PMOS transistor 440 has no effect on the ground bounce problem.
Hence, there is a need for a method or a circuit to suppress noise on a signal line between logic elements. Specifically, the method or circuit must be able to alleviate ground bounce and cross talk noise without significantly slowing the switching time of the logic elements or consuming excessive amounts of board or die area.